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XC2S15 Datasheet

Spartan-ii Fpga

Manufacturer: Xilinx (now AMD)

XC2S15 Overview

DS001-2 (v2.9) March 12, 2021 Architectural Description - Spartan-II Array - Input/Output Block - Configurable Logic Block - Block RAM - Clock Distribution: Delay-Locked Loop - Boundary Scan Development System Configuration - Configuration Timing Design Considerations Module 3: DC and Switching Characteristics DS001-3 (v2.9) March 12, 2021 DC Specifications - Ratings - Remended Operating Conditions - DC...

XC2S15 Key Features

  • General Overview
  • Product Availability
  • User I/O Chart
  • Ordering Information
  • Architectural Description
  • Spartan-II Array
  • Input/Output Block
  • Configurable Logic Block
  • Block RAM
  • Clock Distribution: Delay-Locked Loop

More Datasheets from Xilinx (now AMD)

See all Xilinx (now AMD) datasheets

Part Number Description
XC2S150 Spartan-II FPGA
XC2S150E Spartan-IIE FPGA
XC2S100 Spartan-II FPGA
XC2S100E Spartan-IIE FPGA
XC2S200 Spartan-II FPGA
XC2S200E Spartan-IIE FPGA
XC2S30 Spartan-II FPGA
XC2S300E Spartan-IIE FPGA
XC2S400E Spartan-IIE FPGA
XC2S50 Spartan-II FPGA

XC2S15 Distributor