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XC2S15 - Spartan-II FPGA

General Description

DS001-2 (v2.9) March 12, 2021 Architectural Description - Spartan-II Array - Input/Output Block - Configurable Logic Block - Block RAM - Clock Distribution: Delay-Locked Loop - Boundary Scan Development System Configuration - Configuration Timing Design Consid

Key Features

  • General Overview.
  • Product Availability.
  • User I/O Chart.
  • Ordering Information Module 2: Functional.

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Other Datasheets by Xilinx (now AMD)

Part Number Description
XC2S150 Spartan-II FPGA
XC2S150E Spartan-IIE FPGA
XC2S100 Spartan-II FPGA
XC2S100E Spartan-IIE FPGA
XC2S200 Spartan-II FPGA

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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R Spartan-II FPGA Family Data Sheet DS001 March 12, 2021 Product Specification This document includes all four modules of the Spartan®-II FPGA data sheet. Module 1: Introduction and Ordering Information DS001-1 (v2.9) March 12, 2021 • Introduction • Features • General Overview • Product Availability • User I/O Chart • Ordering Information Module 2: Functional Description DS001-2 (v2.9) March 12, 2021 • Architectural Description - Spartan-II Array - Input/Output Block - Configurable Logic Block - Block RAM - Clock Distribution: Delay-Locked Loop - Boundary Scan • Development System • Configuration - Configuration Timing • Design Considerations Module 3: DC and Switching Characteristics DS001-3 (v2.