XC4004A Datasheet | Xilinx

® XC4000, XC4000A, XC4000H Logic Cell Array Families Product Description Features Description - Third Generation Field-Programmable Gate Arrays - Abundant flip-flops - Flexible function generators - On-chip ultra-fast RAM The XC4000 families of Field-Programmable Gate Arrays (FPGAs) provide the benefits of custom CMOS VLSI, while avoiding the initial cost, time delay, and inherent risk of a conventional masked gate array. - Dedicated high-speed carry-propagation circuit - Wide edge decoders The XC4000 families provide a regular, flexible, programmable architecture of Configurable Logic Blocks (CLBs), - Hierarchy of interconnect lines interconnected by a powerful hierarchy of versatile routing - Internal 3-state bus capability resources, and surrounded by a perimeter of program- - Eight global low-skew clock or signal distribution mable Input/Output Blocks (IOBs). network - Flexible Array Architecture XC4000-family devices have generous routing resources to acmodate the most plex interconnect patterns. - Programmable logic blocks and I/O blocks XC4000A devices have reduced sets of routing resources, - Programmable interconnects and wide decoders sufficient for their smaller size. XC4000H high I/O devices - Sub-micron CMOS Process - High-speed logic and Interconnect maintain the same routing resources and CLB structure as the XC4000 family, while nearly doubling the available I/O. - Low power consumption The devices are customized by loading configuration data - Systems-Oriented Features - IEEE 1149.1-patible boundary-scan logic support - Programmable output slew rate - Programmable input pull-up or pull-down resistors into the internal memory cells. The FPGA can either actively read its configuration data out of external serial or byteparallel PROM (master modes), or the configuration data can be written into the FPGA (slave and peripheral modes). - 12-m A sink current per output (XC4000 family) The XC4000 families are supported...