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XC9572 - XC9572 In-System Programmable CPLD

Datasheet Summary

Features

  • 7.5 ns pin-to-pin logic delays on all pins.
  • fCNT to 125 MHz.
  • 72 macrocells with 1,600 usable gates.
  • Up to 72 user I/O pins.
  • 5V in-system programmable - Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and temperature range.
  • Enhanced pin-locking architecture.
  • Flexible 36V18 Function Block - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, o.

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Datasheet Details

Part number XC9572
Manufacturer Xilinx
File Size 104.19 KB
Description XC9572 In-System Programmable CPLD
Datasheet download datasheet XC9572 Datasheet
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– PRODUCT OBSOLETE / UNDER OBSOLESCENCE – 0 R XC9572 In-System Programmable CPLD DS065 (v5.0) May 17, 2013 05 Features • 7.5 ns pin-to-pin logic delays on all pins • fCNT to 125 MHz • 72 macrocells with 1,600 usable gates • Up to 72 user I/O pins • 5V in-system programmable - Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and temperature range • Enhanced pin-locking architecture • Flexible 36V18 Function Block - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, set and reset signals • Extensive IEEE Std 1149.
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