XCR3032 Datasheet | Xilinx

features of both PLA and PAL type structures to deliver high speed and flexible logic allocation that results in superior ability to make design changes with fixed pinouts. The XPLA structure in each logic block provides a fast 8 ns PAL path with five dedicated product terms per output. This PAL path is joined by an additional PLA structure that deploys a pool of 32 product terms to a fully programmable OR array that can allocate the PLA product terms to any output in the logic block. This bination allows logic to be allocated efficiently throughout the logic block and supports as many as 37 product terms on an output. The speed with which logic is allocated from the PLA array to an output is only 2.5 ns, regardless of the number of PLA product terms used, which results in worst case t PD's of only 10.5 ns from any pin to any other pin. In addition, logic that is mon to multiple outputs can be placed on a single PLA product term and shared across multiple outputs via the OR array, effectively increasing design density. The XCR3032 CPLDs are supported by industry standard CAE tools (Cadence/Or CAD, Exemplar Logic, Mentor, Synopsys, Synario, Viewlogic, and Synplicity), using text (ABEL, VHDL, Verilog) and/or schematic entry. Design verification uses industry standard simulators for functional and timing simulation. Development is supported on personal puter, Sparc, and HP platforms. Device fitting uses a Xilinx developed tool, XPLA Professional (available on the Xilinx web site). The XCR3032 CPLD is reprogrammable using industry standard device programmers from vendors such as Data I/O, BP Microsystems, SMS, and others. Features - - - - - - - - - - - - - - - - - - - Industry's first Total CMOS™ PLD - both CMOS design and process technologies Fast Zero Power (FZP™) design technique provides ultra-low power and very high speed High speed pin-to-pin delays of 8ns Ultra-low static power of less than 35 µA 100% routable with 100% utilization while all pins and all...