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XCR3064A - 64 Macrocell CPLD

Description

The XCR3064A CPLD (Complex Programmable Logic Device) is the second in a family of CoolRunner™ CPLDs from Xilinx.

These devices combine high speed and zero power in a 64 macrocell CPLD.

Features

  • Industry's first TotalCMOS™ PLD - both CMOS design and process technologies.
  • Fast Zero Power (FZP™) design technique provides ultra-low power and very high speed.
  • 3V, In-System Programmable (ISP) using a JTAG interface - On-chip superVoltage generation - ISP commands include: Enable, Erase, Program, Verify - Supported by multiple ISP programming platforms www. DataSheet4U. com - Four pin JTAG interface (TCK, TMS, TDI, TDO) - JTAG commands include: Bypass, Idcode.
  • High sp.

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Part Number Description Manufacturer

Other Datasheets by Xilinx (now AMD)

Part Number Description
XCR3064XL-10CP56C XCR3064XL 64 Macrocell CPLD
XCR3064XL-10CP56I XCR3064XL 64 Macrocell CPLD
XCR3064XL-10CS48C XCR3064XL 64 Macrocell CPLD
XCR3064XL-10CS48I XCR3064XL 64 Macrocell CPLD
XCR3064XL-10PC44C XCR3064XL 64 Macrocell CPLD

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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APPLICATION NOTE 0 R XCR3064A: 64 Macrocell CPLD With Enhanced Clocking 0 14* DS037 (v1.1) February 10, 2000 Product Specification Features Industry's first TotalCMOS™ PLD - both CMOS design and process technologies • Fast Zero Power (FZP™) design technique provides ultra-low power and very high speed • 3V, In-System Programmable (ISP) using a JTAG interface - On-chip superVoltage generation - ISP commands include: Enable, Erase, Program, Verify - Supported by multiple ISP programming platforms www.DataSheet4U.com - Four pin JTAG interface (TCK, TMS, TDI, TDO) - JTAG commands include: Bypass, Idcode • High speed pin-to-pin delays of 7.
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