XCR3064A Overview
The XCR3064A CPLD (plex Programmable Logic Device) is the second in a family of CoolRunner™ CPLDs from Xilinx. These devices bine high speed and zero power in a 64 macrocell CPLD. With the FZP design technique, the XCR3064A offers true pin-to-pin speeds of 7.5 ns, while simultaneously delivering power that is less than 100 µA at standby without the need for "turbo bits" or other power down schemes.
XCR3064A Key Features
- both CMOS design and process technologies
- Fast Zero Power (FZP™) design technique provides ultra-low power and very high speed
- 3V, In-System Programmable (ISP) using a JTAG interface
- On-chip superVoltage generation
- ISP mands include: Enable, Erase, Program, Verify
- Supported by multiple ISP programming platforms
- Four pin JTAG interface (TCK, TMS, TDI, TDO)
- JTAG mands include: Bypass, Idcode
- High speed pin-to-pin delays of 7.5 ns
- Ultra-low static power of less than 100 µA