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XCR5128 - 128 Macrocell CPLD

General Description

The XCR5128 CPLD (Complex Programmable Logic Device) is the third in a family of CoolRunner® CPLDs from Xilinx.

These devices combine high speed and zero power in a 128 macrocell CPLD.

Key Features

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  • Industry's first TotalCMOS™ PLD - both CMOS design and process technologies Fast Zero Power (FZP™) design technique provides ultra-low power and very high speed IEEE 1149.1-compliant, JTAG Testing Capability - Four pin JTAG interface (TCK, TMS, TDI, TDO) - IEEE 1149.1 TAP Controll.

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Full PDF Text Transcription for XCR5128 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for XCR5128. For precise diagrams, and layout, please refer to the original PDF.

APPLICATION NOTE DS041 (v1.2) August 10, 2000 Features • • w • • w • • • • • • • • • • • • • • • • • Industry's first TotalCMOS™ PLD - both CMOS design and process techno...

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Industry's first TotalCMOS™ PLD - both CMOS design and process technologies Fast Zero Power (FZP™) design technique provides ultra-low power and very high speed IEEE 1149.1-compliant, JTAG Testing Capability - Four pin JTAG interface (TCK, TMS, TDI, TDO) - IEEE 1149.1 TAP Controller - JTAG commands include: Bypass, Sample/Preload, Extest, Usercode, Idcode, HighZ 5V, In-System Programmable (ISP) using the JTAG interface - On-chip supervoltage generation - ISP commands include: Enable, Erase, Program, Verify - Supported by multiple ISP programming platforms High speed pin-to-pin delays of 7.