XCR5128 Overview
The XCR5128 CPLD (plex Programmable Logic Device) is the third in a family of CoolRunner® CPLDs from Xilinx. These devices bine high speed and zero power in a 128 macrocell CPLD. With the FZP design technique, the XCR5128 offers true pin-to-pin speeds of 7.5 ns, while simultaneously delivering power that is less than 100 µA at standby without the need for ‘turbo bits' or other power down schemes.
XCR5128 Key Features
- Industry's first TotalCMOS™ PLD
- both CMOS design and process technologies Fast Zero Power (FZP™) design technique provides ultra-low power and very high
- Four pin JTAG interface (TCK, TMS, TDI, TDO)
- IEEE 1149.1 TAP Controller
- JTAG mands include: Bypass, Sample/Preload, Extest, Usercode, Idcode, HighZ 5V, In-System Programmable (ISP) using the J
- On-chip supervoltage generation
- ISP mands include: Enable, Erase, Program, Verify
- Programmable 3-state buffer
- Asynchronous macrocell register preset/reset Programmable global 3-state pin facilitates "bed of nails" testing without