XQR18V04 Datasheet | Xilinx

QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs DS082 (v1.2) November 5, 2001 Preliminary Product Specification Features - In-system programmable 3.3V PROMs for configuration of Xilinx FPGAs - - - Endurance of 2,000 program/erase cycles Program/erase over full military temperature range Radiation Hardenned XQR18V04 - - - - Fabricated on Epitaxial Substrate Latch-Up Immune to >120 LET Guaranteed TID of 40 k Rad(Si) Supports SEU Scrubbing IEEE Std 1149.1 boundary-scan (JTAG) support Cascadable for storing longer or multiple bitstreams Dual configuration modes Serial Slow/Fast configuration (up to 33 MHz) Parallel (up to 264 Mbps at 33 MHz) Description Xilinx introduces the QPro™ XQ18V04 and XQR18V04 series of QML in-system programmable and radiation hardened configuration PROMs. Initial devices in this 3.3V family are a 4-megabit PROM that provide an easy-to-use, cost-effective method for re-programming and storing large Xilinx FPGA configuration bitstreams. When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM. A short access time after the rising CCLK, data is available on the PROM DATA (D0) pin that is connected to the FPGA DIN pin. The FPGA generates the appropriate number of clock pulses to plete the configuration. When the FPGA is in Slave Serial mode, the PROM and the FPGA are clocked by an external clock. When the FPGA is in Express or Select MAP Mode, an external oscillator will generate the configuration clock that drives the PROM and the FPGA. After the rising CCLK edge, data are available on the PROMs DATA (D0-D7) pins. The data will be clocked into the FPGA on the following rising edge of the CCLK. Neither Express nor Select MAP utilize a Length Count, so a free-running oscillator may be used. See Figure 6. OE/Reset - - - - - - - Low-power advanced CMOS FLASH process 5V tolerant I/O pins accept 5V, 3.3V and 2.5V signals. 3.3V or 2.5V output capability Available in CC44...