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ZL30409 Datasheet T1/e1 System Synchronizer With Stratum 3 Holdover

Manufacturer: Zarlink Semiconductor Inc

Overview: ZL30409 T1/E1 System Synchronizer with Stratum 3 Holdover Data.

Datasheet Details

Part number ZL30409
Manufacturer Zarlink Semiconductor Inc
File Size 483.77 KB
Description T1/E1 System Synchronizer with Stratum 3 Holdover
Datasheet ZL30409_ZarlinkSemiconductorInc.pdf

General Description

The ZL30409 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links.

The ZL30409 generates ST-BUS clock and framing signals that are phase locked to either a 19.44 MHz, 2.048MHz, 1.544MHz, or 8kHz input reference.

OSCi OSCo TCLR LOCK VDD GND Master Clock TCK TDI TMS TRST TDO PRI SEC IEEE 1149.1a TIE Corrector Circuit Selected Reference Reference Select MUX Reference Select TIE Corrector Enable Virtual Reference DPLL Output Interface Circuit State Select Input Impairment Monitor State Select C19o C1.5o C2o C4o C6o C8o C16o F0o F8o F16o RSP TSP RSEL Control State Machine Feedback Frequency Select MUX MS1 MS2 RST HOLDOVER PCCi FLOCK FS1 FS2 Figure 1 - Functional Block Diagram Zarlink Semiconductor US Patent No.

Key Features

  • Supports Telcordia GR-1244-CORE Stratum 4 timing for DS1 interfaces Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interfaces Selectable 19.44 MHz, 2.048MHz, 1.544MHz or 8kHz input reference signals Provides C1.5, C2, C4, C6, C8, C16, and C19 (STS-3/OC3 clock divided by 8) output clock signals Provides 5 styles of 8 KHz framing pulses Holdover frequency accuracy of 0.05 PPM Holdover indication Attenuates wander from 1.9Hz Fast lock mode.

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