MT8952B Description
The MT8952B HDLC Protocol Controller frames and formats data packets according to X.25 (Level 2) Remendations from the CCITT. D0-D7 A0-A3 R/W CS E IRQ WD VDD VSS RST C-Channel Interface Micro Processor Interface Transmit FIFO Transmit Logic Zero Insertion Flag/Abort Generator TEOP CDSTo Address Decoder Interrupt Registers Control and Status Register Timing Logic F0i CKi RxCEN TxCEN Receive FIFO Receive Logic Address...
MT8952B Key Features
- Formats data as per X.25 (CCITT) level-2 standards
- Go-Ahead sequence generation and detection
- Single byte address recognition
- Microprocessor port and directly accessible
- 19 byte FIFO in both send and receive paths
- Handshake signals for multiplexing data links
- High speed serially clocked output (2.5 Mbps)
- ST-BUS patibility with programmable channel
- Independent watchdog timer
- Facility to disable protocol functions