MT8952B Datasheet | Zarlink Semiconductor

Features - Formats data as per X.25 (CCITT) level-2 standards - Go-Ahead sequence generation and detection - Single byte address recognition - Microprocessor port and directly accessible registers for flexible operation and control - 19 byte FIFO in both send and receive paths - Handshake signals for multiplexing data links - High speed serially clocked output (2.5 Mbps) - ST-BUS patibility with programmable channel selection for data and separate timeslot for control information - Independent watchdog timer - Facility to disable protocol functions - Low power ISO-CMOS technology Applications - Data link controllers and protocol generators August 2011 Ordering Information MT8952BE1 MT8952BP1 MT8952BPR1 MT8952BS1 28 Pin PDIP- 28 Pin PLCC- 28 Pin PLCC- 28 Pin SOIC- Tubes Tubes Tape & Reel Tubes - Pb Free Matte Tin -40C to +85C - Digital sets, PBXs and private packet networks - D-channel controller for ISDN basic access - C-channel controller to Digital Network Interface Circuits...