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MT8952B Datasheet Hdlc Protocol Controller

Manufacturer: Zarlink Semiconductor

Overview: ISO-CMOS ST-BUSTM Family MT8952B HDLC Protocol Controller Data.

General Description

The MT8952B HDLC Protocol Controller frames and formats data packets according to X.25 (Level 2) Remendations from the CCITT.

D0-D7 A0-A3 R/W CS E IRQ WD VDD VSS RST C-Channel Interface Micro Processor Interface Transmit FIFO Transmit Logic Zero Insertion Flag/Abort Generator TEOP CDSTo Address Decoder Interrupt Registers Control and Status Register Timing Logic F0i CKi RxCEN TxCEN Receive FIFO Receive Logic Address Detection Zero Deletion Flag/Abort/ Idle Detection Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

Key Features

  • Formats data as per X.25 (CCITT) level-2 standards.
  • Go-Ahead sequence generation and detection.
  • Single byte address recognition.
  • Microprocessor port and directly accessible registers for flexible operation and control.
  • 19 byte FIFO in both send and receive paths.
  • Handshake signals for multiplexing data links.
  • High speed serially clocked output (2.5 Mbps).
  • ST-BUS compatibility with programmable channel selection for data and.

Similar Datasheet

Brand Logo Part Number Description Manufacturer
Mitel Networks Corporation Logo MT8952B HDLC Protocol Controller Mitel Networks Corporation

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MT8952B Distributor