MT9074 Datasheet | Zarlink Semiconductor

Features - bined E1 (PCM30) and T1 (D4/ESF) framer, Line Interface Unit (LIU) and link controller with optional digital framer only mode In T1 mode the LIU can recover signals attenuated by up to 30 d B (5000 ft. of 24 AWG cable) In E1 mode the LIU can recover signals attenuated by up to 30 d B (1900 m. of 0.65 mm cable) Two HDLCs: FDL and channel 24 in T1 mode, timeslot 0 (Sa bits) and timeslot 16 in E1 mode Two-frame elastic buffer in Rx & Tx (T1) directions Programmable transmit delay through transmit slip buffer Low jitter DPLL for clock generation Enhanced alarms, performance monitoring and error insertion functions Intel or Motorola non-multiplexed parallel microprocessor interface ST-BUS 2.048 Mbit/s backplane bus for both data and signaling Japan Tele J1 Framing and Yellow Alarm Tx DL Tx DLCLK Tx MF August 2005 Ordering Information MT9074AL MT9074AP MT9074APR MT9074AL1 MT9074AP1 MT9074APR1 100 Pin MQFP 68 Pin PLCC 68 Pin PLCC 100 Pin MQFP- 68 Pin PLCC- 68 Pin PLCC- - Pb Free Matte Tin -40 ° C to +85 ° C Trays Tubes Tape & Reel Trays Tubes Tape & Reel - - - - - - - - - - - - Hardware data link access JTAG Boundary Scan Applications - - - - - E1/T1 add/drop multiplexers and channel banks CO and PBX equipment interfaces Primary Rate ISDN nodes Digital Cross-connect Systems (DCS) MT9074A was revised after its market introduction. Software can confirm that the installed chip is the most recent revision of MT9074A as follows: 1. In T1 mode, the LSB (Least Significant Bit) of the Synchronization Status Word - bit 0, Page 3 Address 10H is set high. Batch codes 61755.0 or higher, and/or date code beginning with 00, 01, 02, etc. Tx AO Tx B Tx A 2. DSTi CSTi Tdi Tdo Tms Tclk Trst ST-BUS Interface IEEE 1149.1 Transmit Framing, Error, Test Signal Generation and Slip Buffer Pulse Generator Line Driver TTIP TRING RM Loop National Bit Buffer Data Link, HDLC0 HDLC1 Jitter Attenuator & Clock Control CAS Buffer MT Loop ST Loop PL Loop CS DS/RD DSTo CSTo Clock,Data...