Datasheet Details
| Part number | PDSP16116A |
|---|---|
| Manufacturer | Zarlink Semiconductor |
| File Size | 174.85 KB |
| Description | 16 by 16 Bit Complex Multiplier |
| Datasheet |
 PDSP16116A Datasheet
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General Description
16 bit input for real x data 16 bit input for imag x data 16 bit input for reaal y data 16 bit input for imag y data 16 bit output for real p data 16 bit output for img p data Clock, new data is loaded on rising edge of CLK Clock, enable X-port input register Clock, enable Y-port input register Conj
Key Features
- s s s s s s s s s s Complex Number (16 + 16) X (16 + 16) Multiplication Full 32 bit Result 20MHz Clock Rate Block Floating Point FFT Butterfly Support -1 times -1 Trap Two's Complement Fractional Arithmetic TTL Compatible I/O Complex Conjugation 2 Cycle Fall Through 144 pin PGA or QFP packages MULT MULT MULT MULT REG REG REG REG.