SP8861 Datasheet | Zarlink Semiconductor

feature . LOCK DETECT PD1 OUTPUT FPD- VEE3 27 26 25 24 23 FREF- POWER DOWN VEE4 VCC4 VCC1 RF INPUT RF INPUT Cd 5 6 7 8 9 10 11 12 13 14 15 16 17 18 PD2 OUTPUT RPD VCC3 GROUND XTAL 1 XTAL2 VEE2 22 21 20 19 FEATURES s Improved Digital Phase Detector Eliminates HP28 ‘Dead Band’ Effects s Low Operating Power, Typically 175m W - FPD and FREF outputs are reversed by the phase detector sense bit in the F1/F2 programming word. The s 1- 3GHz Operating Frequency above diagram is correct when the sense bit is low. See s plete Phase Locked Loop Table 2 and Fig. 7. s High Input Sensitivity VCC1, VEE1 - preamplifier and prescaler supplies s Programmed through Three-Wire Bus .. VCC2, VEE2 - oscillator supplies s Wide Range of Reference Division Ratios VCC3, VEE3 - charge pump 2 supplies s Local Storage for Two Frequency Words, giving VCC4, VEE4 - ECL supplies Rapid Frequency Toggling s Programmable Phase Detector Gain Fig. 1 Pin identification diagram (top view) s Power Down Mode DATA CLOCK ENABLE F1/F2 VEE1 NC ABSOLUTE MAXIMUM RATINGS Supply voltage Storage temperature Operating temperature Prescaler input voltage 20- 3V to 17V 255°C to 1150°C 240°C to 185°C 2- 5V p-p ORDERING INFORMATION SP8861/NA/HP VCC2 RF INPUT RF INPUT 10 11 16/17 OR 8/9 CONTROL A COUNT 1LOGIC M COUNT 1LOGIC f PD PHASE DETECTOR LOGIC F1/F2 DATA CLOCK ENABLE 13 14 4 BIT 15...