SP8861 Datasheet PDF - Zarlink Semiconductor Low Power Single-Chip Frequency Synthesiser Specs

SP8861 - Low Power Single-Chip Frequency Synthesiser

Datasheet Summary

Description

The programmable divider chain is of AM counter design and therefore contains a dual modulus front end prescaler, an A counter which controls the dual modulus ratio and an M counter which controls the bulk multi-modulus division.

Features

s Improved Digital Phase Detector Eliminates HP28 ‘Dead Band’ Effects s Low Operating Power, Typically 175mW.
FPD and FREF outputs are reversed by the phase detector sense bit in the F1/F2 programming word. The s 1.
3GHz Operating Frequency above diagram is correct when the sense bit is low. See s Complete Phase Locked Loop Table 2 and Fig. 7. s High Input Sensitivity VCC1, VEE1.
preamplifier and prescaler supplies s Programmed throughThree-Wire Bus www. DataSheet4U. com VCC2, VEE2.

Datasheet Details

Part number	SP8861
Manufacturer	Zarlink Semiconductor
File Size	308.01 KB
Description	Low Power Single-Chip Frequency Synthesiser
Datasheet	SP8861 Datasheet
Additional preview pages of the SP8861 datasheet.

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Full PDF Text Transcription

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SP8861 1·3GHz Low Power Single-Chip Frequency Synthesiser Supersedes version in the1996 Professional Products IC Handbook, HB2480 - 3.0 DS3640 - 4.0 April 1998 The SP8861 is a low power single chip synthesiser intended for professional radio applications, containing all the elements (apart from the loop amplifier) required to build a PLL frequency synthesis loop The device is serially programmable by a three-wire data highway and contains three independent buffers to store one reference divider word and two local oscillator divider words. A digital phase detector with two charge pumps, programmable in phase and gain, are provided to improve lock-up performance.

Published: Apr 17, 2007 |