ZL50012 Datasheet | Zarlink Semiconductor

ZL50012 Flexible 512-ch Digital Switch Data Sheet Features - 512 channel x 512 channel non-blocking switch at 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s operation - Rate conversion between the ST-BUS inputs and ST-BUS outputs - Per-stream ST-BUS input with data rate selection of 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s - Per-stream ST-BUS output with data rate selection of 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s; the output data rate can be different than the input data rate - Per-stream high impedance control output for every ST-BUS output with fractional bit advancement - Per-stream input channel and input bit delay programming with fractional bit delay - Per-stream output channel and output bit delay programming with fractional bit advancement - Multiple frame pulse outputs and reference clock outputs - Per-channel constant throughput delay April 2006 Ordering Information ZL50012/QCC 160 Pin LQFP Trays ZL50012/GDC 144 Ball LBGA Trays ZL50012QCG1 160 Ball LQFP- Trays, Bake & Drypack ZL50012GDG2 144 Ball LBGA- - Trays, Bake & Drypack - Pb Free Matte Tin - - Pb Free Tin/Silver/Copper -40°C to +85°C - Per-channel high impedance output control - Per-channel message mode - Per-channel pseudo random bit sequence (PRBS) pattern generation and bit error detection - Control interface patible to Motorola nonmultiplexed CPUs - Connection memory block programming capability - IEEE-1149.1 (JTAG) test port - 3.3V I/O with 5 V tolerant input RESET STi0-15 S/P Converter Data Memory P/S...