ZL50110 Overview
ZL50110/11/14 128, 256 and 1024 Channel CESoP Processors Data Sheet.
ZL50110 Key Features
- Circuit Emulation Services over Packet (CESoP) transport for MPLS, IP and Ethernet networks On chip timing & synchroniza
- 40°C to +85°C Direct connection to LIUs, framers, backplanes Dual reference Stratum 3, 4 and 4E DPLL for synchronous ope
- plies with ITU-T remendation Y.1413 plies with IETF PWE3 draft standards for CESoPSN and SAToP plies with CESoP draft IA
- Up to 3 x 100 Mbps MII Fast Ethernet or Dual Redundant 1000 Mbps GMII/TBI Ethernet Interfaces
- Flexible 32 bit host CPU interface (Motorola PowerQUICC™ patible) On-chip packet memory for self-contained operation, wi
- 8 Mbytes)
- ZL50110/11/14 High Level Overview 1
- Data Sheet