ZL50410 Overview
ZL50410 Managed 8-Port 10/100M + 1-Port 10/100/1000M Ethernet Switch Data Sheet Features 8/16-bit or Serial MII GMII / MII 8-Port 10/100M + 1G Ethernet Switch I2C 10/100/ 1000 PHY RMII / MII / GPSI Quad 10/100 PHY Quad 10/100 PHY Figure 1 - System Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved. ZL50410 Data Sheet • link failover in less than 50 ms Rate Control (both ingress and egress) • Bandwidth rationing, Bandwidth on demand, SLA (Service Level Agreement) • Smooth out traffic to uplink port • Ingress Rate Control - Back pressure - Flow Control - WRED (Weighted Random Early Discard) • Egress Rate Control • Down to 16 kbps Rate Control granularity • Per queue traffic shaper on uplink port • Packet Filtering and Port Security • Static...
ZL50410 Key Features
- Eight 10/100 Mbps auto-negotiating Fast Ethernet (FE) ports with RMII, MII, GPSI, Reverse MII & Reverse GPSI interface o
- One 10/100/1000 Mbps auto-negotiating port with GMII & MII interface options, that can be used as a WAN uplink or as a 9
- a 10/100 Mbps Fast Ethernet (FE) CPU port with Reverse MII interface option
- Operates stand-alone or can be cascaded with a second ZL50410 to reach 16 ports
- Embedded 2 Mbits (256 KBytes) internal memory
- supports up to 4 K byte frames
- L2 switching
- MAC address self learning, up to 4 K MAC addresses using internal table
- Supports IP Multicast with IGMP snooping, up to 4 K IP Multicast groups
- Supports the following spanning standards