Description
The ZL30106 SONET/SDH/PDH network interface Digital Phase-Locked Loop (DPLL) provides timing and synchronization for SONET/SDH and PDH network interface cards.
Features
- Synchronizes to clock-and-sync-pair to maintain minimal phase skew between inputs and outputs.
- Supports output wander and jitter generation specifications for SONET/SDH and PDH interfaces.
- Accepts three input references and synchronizes to any combination of 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz inputs.
- Provides a range of clock outputs: - 2.048 MHz (E1), 16.384 MHz and either 4.096 MHz and 8.192 MHz or 32.768 MHz and 65.536 M.
ZL30106 Datasheet
