ZL30106 Overview
The ZL30106 SONET/SDH/PDH network interface Digital Phase-Locked Loop (DPLL) provides timing and synchronization for SONET/SDH and PDH network interface cards. The ZL30106 generates SONET/SDH, PDH, ST-BUS and other TDM clock and framing signals that are phase locked to one of three network references. It helps ensure system reliability by monitoring its references for frequency accuracy and stability and by...
ZL30106 Key Features
- Synchronizes to clock-and-sync-pair to maintain minimal phase skew between inputs and outputs
- Supports output wander and jitter generation specifications for SONET/SDH and PDH interfaces
- Accepts three input references and synchronizes to any bination of 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384
- Provides a range of clock outputs
- 2.048 MHz (E1), 16.384 MHz and either 4.096 MHz and 8.192 MHz or 32.768 MHz and 65.536 MHz
- 19.44 MHz (SONET/SDH)
- 1.544 MHz (DS1) and 3.088 MHz
- Provides 5 styles of 8 kHz framing pulses and a 2 kHz multi-frame pulse
- Provides automatic entry into Holdover and return from Holdover
- Manual and automatic hitless reference switching between any bination of valid input reference frequencies
ZL30106 Applications
- Line card synchronization for SONET/SDH and PDH systems