A2V64S40CTP Overview
Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
A2V64S40CTP Key Features
- 3.3V power supply LVTTL patible with multiplexed address Four banks operation MRS cycle with address key programs
- CAS latency (2 & 3)
- Burst length (1, 2, 4, 8 & Full page)
- Burst type (Sequential & Interleave)
- All inputs are sampled at the positive going edge of the system clock Auto & self refresh 64ms refresh period (4K cycle)
