A3S56D40ETP Overview
All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe ,and output data and data strobe are referenced on both edges of CLK. The A3S56D30/40ETP achieves very high speed clock rate up to 200 MHz.
A3S56D40ETP Key Features
- Vdd=Vddq=2.5V+0.2V (-5E, -5, -6)
- Double data rate architecture ; two data transfers per clock cycle
- Bidirectional , data strobe (DQS) is transmitted/received with data
- Differential clock input (CLK and /CLK)
- DLL aligns DQ and DQS transitions with CLK transitions edges of DQS
- mands entered on each positive CLK edge
- Data and data mask referenced to both edges of DQS
- 4 bank operation controlled by BA0 , BA1 (Bank Address)
- /CAS latency
- 2.0 / 2.5 / 3.0 (programmable) ; Burst length