A3S56D40ETP - (A3S56D30ETP / A3S56D40ETP) 256Mb DDR SDRAM

Product Overview

Zentel

Datasheet Details

Part number	A3S56D40ETP
Manufacturer	Zentel
File Size	952.32 KB
Description	(A3S56D30ETP / A3S56D40ETP) 256Mb DDR SDRAM
Datasheet	A3S56D40ETP Datasheet
Additional preview pages of the A3S56D40ETP datasheet.

Product details

Description

A3S56D30ETP is a 4-bank x 8,388,608-word x 8bit, A3S56D40ETP is a 4-bank x 4,194,304-word x 16bit double data rate synchronous DRAM , with SSTL_2 interface.

Features

- Vdd=Vddq=2.5V+0.2V (-5E, -5, -6) - Double data rate architecture ; two data transfers per clock cycle. - Bidirectional , data strobe (DQS) is transmitted/received with data - Differential clock input (CLK and /CLK) - DLL aligns DQ and DQS transitions with CLK transitions edges of DQS - Commands entered on each positive CLK edge ; - Data and data mask referenced to both edges of DQS - 4 bank operation controlled by BA0 , BA1 (Bank Address) - /CAS latency - 2.0 / 2.5 / 3.0 (programmable) ; Burst.

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Published: Sep 1, 2009 |