Datasheet Details
| Part number | A3S56D40FTP |
|---|---|
| Manufacturer | Zentel |
| File Size | 201.31 KB |
| Description | 256M Double Data Rate Synchronous DRAM |
| Datasheet |
 A3S56D40FTP Datasheet
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General Description
A3S56D30FTP is a 4-bank x 8,388,608-word x 8bit, A3S56D40FTP is a 4-bank x 4,194,304-word x 16bit double data rate synchronous DRAM , with SSTL_2 interface.
All control and address signals are referenced to the rising edge of CLK.
Key Features
- - Vdd=VddQ=2.5V+0.2V (-4, -5E, -5) - Double data rate architecture ; two data transfers per clock cycle. - Bidirectional , data strobe (DQS) is transmitted/received with data - Differential clock input (CLK and /CLK) - DLL aligns DQ and DQS transitions with CLK transitions edges of DQS - Commands entered on each positive CLK edge ; - Data and data mask referenced to both edges of DQS - 4 bank operation controlled by BA0 , BA1 (Bank Address) - /CAS latency - 2.0 / 2.5 / 3.0 / 4.0 (programmable) ;.