A3S56D40FTP - 256M Double Data Rate Synchronous DRAM

This page provides the datasheet information for the A3S56D40FTP, a member of the A3S56D30FTP 256M Double Data Rate Synchronous DRAM family.

Datasheet Summary

Description

A3S56D30FTP is a 4-bank x 8,388,608-word x 8bit, A3S56D40FTP is a 4-bank x 4,194,304-word x 16bit double data rate synchronous DRAM , with SSTL_2 interface.

All control and address signals are referenced to the rising edge of CLK.

Features

- Vdd=VddQ=2.5V+0.2V (-4, -5E, -5) - Double data rate architecture ; two data transfers per clock cycle. - Bidirectional , data strobe (DQS) is transmitted/received with data - Differential clock input (CLK and /CLK) - DLL aligns DQ and DQS transitions with CLK transitions edges of DQS - Commands entered on each positive CLK edge ; - Data and data mask referenced to both edges of DQS - 4 bank operation controlled by BA0 , BA1 (Bank Address) - /CAS latency - 2.0 / 2.5 / 3.0 / 4.0 (programmable) ;.

Zentel

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Datasheet Details

Part number	A3S56D40FTP
Manufacturer	Zentel
File Size	201.31 KB
Description	256M Double Data Rate Synchronous DRAM
Datasheet	A3S56D40FTP Datasheet
Additional preview pages of the A3S56D40FTP datasheet.

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Full PDF Text Transcription

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A3S56D30FTP A3S56D40FTP 256M Double Data Rate Synchronous DRAM 256Mb DDR SDRAM Specification A3S56D30FTP A3S56D40FTP Zentel Electronics Corp. Revision 1.3 Apr., 2010 A3S56D30FTP A3S56D40FTP 256M Double Data Rate Synchronous DRAM DESCRIPTION A3S56D30FTP is a 4-bank x 8,388,608-word x 8bit, A3S56D40FTP is a 4-bank x 4,194,304-word x 16bit double data rate synchronous DRAM , with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe ,and output data and data strobe are referenced on both edges of CLK. The A3S56D30/40FTP achieves very high speed clock rate up to 250 MHz . FEATURES - Vdd=VddQ=2.5V+0.2V (-4, -5E, -5) - Double data rate architecture ; two data transfers per clock cycle.

Published: Nov 23, 2014 |