Texas Instruments 74AC11162
the 74AC11162 is synchronous, and a low level at the clear (CLR) input drives all four of the flip-flop outputs low after the next low-to-high transition of the clock regardless of the levels on the count-enable (ENP and ENT) inputs. This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The active-low output of the gate used for decoding is connected to the clear input to synchronously clear the counter to 0000 (LLLL on the Q outputs).| Part No. | 74AC11162 |
|---|---|
| Datasheet | 74AC11162 Download |
| Manufacturer |  Texas Instruments |
| Description | SYNCHRONOUS 4-BIT DECADE COUNTER |
| Buy | Stock & Price |
74AC11162 SYNCHRONOUS 4-BIT DECADE COUNTER
● Internal Look-Ahead Circuitry for Fast Counting
● Carry Output for N-Bit Cascading
● Fully Synchronous Operation for Counting
● Synchronously Programmable
● Flow-Through Architecture Optimizes PCB Layout
● Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise
● EPIC ™ (Enhanced-Performance Implanted CMOS) 1-µm Process
● 500-mA Typical Latch-Up Immunity at 125°C
● Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs SCAS381 – D3199, AUGUST 1988 – REVISED APRIL 1993 DW OR N PACKAGE (TOP VIEW) RCO QA QB GND GND GND GND QC QD LOAD 1 2 3 4 5 6 7 8 9 10 20 CLR 19 CLK 18 A 17 B 16 VCC 15 VCC 14 C 13 D 12 ENP 11 ENT description This synchronous, presettable 4-bit decade counter features an internal carry look-ahead circuitry for application in high-speed counting designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating.
● Internal Look-Ahead Circuitry for Fast Counting
● Carry Output for N-Bit Cascading
● Fully Synchronous Operation for Counting
● Synchronously Programmable
● Flow-Through Architecture Optimizes PCB Layout
● Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise
● EPIC ™ (Enhanced-Performance Implanted CMOS) 1-µm Process
● 500-mA Typical Latch-Up Immunity at 125°C
● Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs SCAS381 – D3199, AUGUST 1988 – REVISED APRIL 1993 DW OR N PACKAGE (TOP VIEW) RCO QA QB GND GND GND GND QC QD LOAD 1 2 3 4 5 6 7 8 9 10 20 CLR 19 CLK 18 A 17 B 16 VCC 15 VCC 14 C 13 D 12 ENP 11 ENT description This synchronous, presettable 4-bit decade counter features an internal carry look-ahead circuitry for application in high-speed counting designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating.
