Texas Instruments 74AC11280
The 74AC11280 is characterized for operation from – 40°C to 85°C.| Part No. | 74AC11280 |
|---|---|
| Datasheet | 74AC11280 Download |
| Manufacturer |  Texas Instruments |
| Description | 9-BIT PARITY GENERATOR/CHECKER |
| Buy | Stock & Price |
74AC11280 9-BIT PARITY GENERATOR/CHECKER
● Generates Either Odd or Even Parity for Nine Data Lines
● Cascadable for n-Bits Parity
● Flow-Through Architecture to Optimize PCB Layout
● Center-Pin VCC and GND Configurations to Minimize High-Speed Switching Noise t● EPIC (Enhanced-Performance Implanted CMOS) 1-mm Process
● 500-mA Typical Latch-Up Immunity at 125°C
● Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs SCAS055A – D3201, APRIL 1989 – REVISED APRIL 1993 D OR N PACKAGE (TOP VIEW) B A Σ ODD GND Σ EVEN NC I 1 2 3 4 5 6 7 14 C 13 D 12 E 11 VCC 10 F 9G 8H description This universal, monolithic, nine-bit parity generator/checker features odd and even outputs to facilitate operation of either odd or even parity application. The word-length capability is easily expanded by cascading. FUNCTION TABLE NUMBER OF INPUTS A THRU I THAT ARE HIGH OUTPUTS S EVEN S ODD 0, 2, 4, 6, 8 HL 1, 3, 5, 7, 9 LH logic symbol† 2 A 1 B 14 C 13 D 12 E 10 F 9 G 8 H 7 I 2k 5 Σ EVEN 3 Σ ODD † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
● Generates Either Odd or Even Parity for Nine Data Lines
● Cascadable for n-Bits Parity
● Flow-Through Architecture to Optimize PCB Layout
● Center-Pin VCC and GND Configurations to Minimize High-Speed Switching Noise t● EPIC (Enhanced-Performance Implanted CMOS) 1-mm Process
● 500-mA Typical Latch-Up Immunity at 125°C
● Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs SCAS055A – D3201, APRIL 1989 – REVISED APRIL 1993 D OR N PACKAGE (TOP VIEW) B A Σ ODD GND Σ EVEN NC I 1 2 3 4 5 6 7 14 C 13 D 12 E 11 VCC 10 F 9G 8H description This universal, monolithic, nine-bit parity generator/checker features odd and even outputs to facilitate operation of either odd or even parity application. The word-length capability is easily expanded by cascading. FUNCTION TABLE NUMBER OF INPUTS A THRU I THAT ARE HIGH OUTPUTS S EVEN S ODD 0, 2, 4, 6, 8 HL 1, 3, 5, 7, 9 LH logic symbol† 2 A 1 B 14 C 13 D 12 E 10 F 9 G 8 H 7 I 2k 5 Σ EVEN 3 Σ ODD † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
