74AC11648 Datasheet | Texas Instruments

description 74AC11648 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCAS114 - MARCH 1990 - REVISED APRIL 1993 DW OR NT PACKAGE (TOP VIEW) OE A1 A2 A3 A4 GND GND GND GND A5 A6 A7 A8 DIR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 CLKAB 27 SAB 26 B1 25 B2 24 B3 23 B4 22 VCC 21 VCC 20 B5 19 B6 18 B7 17 B8 16 CLKBA 15 SBA The 74AC11648 consists of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the 74AC11648. Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either register or in both. The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The direction control (DIR) determines which bus will receive data when OE is low. In the isolation mode (OE high), A data may be stored in one register and/or B data may be stored in the other register. When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses, A or B, may be driven at a time. The 74AC11648 is characterized for operation from - 40°C to 85°C. EPIC is a trademark of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. - POST OFFICE BOX 655303 DALLAS, TEXAS 75265 Copyright © 1993, Texas Instruments Incorporated 2- 1 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCAS114 - MARCH...