Texas Instruments 74AC11873
The 74AC11873 is characterized for operation from – 40°C to 85°C.| Part No. | 74AC11873 |
|---|---|
| Datasheet | 74AC11873 Download |
| Manufacturer |  Texas Instruments |
| Description | DUAL 4-BIT D-TYPE LATCH |
| Buy | Stock & Price |
74AC11873 DUAL 4-BIT D-TYPE LATCH WITH 3-STATE OUTPUTS SCAS095 – JANUARY 1990 – REVISED APRIL 1993
● 3-State Buffer-Type Outputs Drive Bus Lines Directly
● Bus-Structured Pinout
● Flow-Through Architecture Optimizes PCB Layout
● Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise
● EPIC™ (Enhanced-Performance Implanted CMOS) 1-µm Process
● 500-mA Typical Latch-Up Immunity at 125°C description This dual 4-bit transparent D-type latch features 3-state outputs designed specifically for bus driving. This makes these devices particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. DW PACKAGE (TOP VIEW) 1LE 1Q1 1Q2 1Q3 1Q4 GND GND GND GND 2Q1 2Q2 2Q3 2Q4 2LE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 1OC 27 1CLR 26 1D1 25 1D2 24 1D3 23 1D4 22 VCC 21 VCC 20 2D1 19 2D2 18 2D3 17 2D4 16 2CLR 15 2OC When the latch-enable (1LE or 2LE) input is high, the Q outputs will follow the data (D) inputs in true form, according to the function table.
● 3-State Buffer-Type Outputs Drive Bus Lines Directly
● Bus-Structured Pinout
● Flow-Through Architecture Optimizes PCB Layout
● Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise
● EPIC™ (Enhanced-Performance Implanted CMOS) 1-µm Process
● 500-mA Typical Latch-Up Immunity at 125°C description This dual 4-bit transparent D-type latch features 3-state outputs designed specifically for bus driving. This makes these devices particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. DW PACKAGE (TOP VIEW) 1LE 1Q1 1Q2 1Q3 1Q4 GND GND GND GND 2Q1 2Q2 2Q3 2Q4 2LE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 1OC 27 1CLR 26 1D1 25 1D2 24 1D3 23 1D4 22 VCC 21 VCC 20 2D1 19 2D2 18 2D3 17 2D4 16 2CLR 15 2OC When the latch-enable (1LE or 2LE) input is high, the Q outputs will follow the data (D) inputs in true form, according to the function table.
