ADC14C105 Datasheet | Texas Instruments

FEATURES - 2 1 GHz Full Power Bandwidth - Internal Reference and Sample-and-Hold Circuit - Low Power Consumption - Data Ready Output Clock - Clock Duty Cycle Stabilizer - Single +3.0V or +3.3V Supply Operation - Power-Down Mode - 32-pin WQFN Package, (5x5x0.8mm, 0.5mm pin-pitch) APPLICATIONS - High IF Sampling Receivers - Wireless Base Station Receivers - Test and Measurement Equipment - munications Instrumentation - Portable Instrumentation KEY SPECIFICATIONS - Resolution: 14 Bits - Conversion Rate: 105 MSPS - SNR (f IN = 240 MHz): 71 d BFS (typ) - SFDR (f IN = 240 MHz): 82 d BFS (typ) - Full Power Bandwidth: 1 GHz (typ) - Power Consumption - 350 m W (typ, VA=3.0V) - 400 m W (typ, VA=3.3V) DESCRIPTION The ADC14C105 is a high-performance CMOS analog-to-digital converter capable of converting analog input signals into 14-bit digital words at rates up to 105 Mega Samples Per Second (MSPS). This converter uses a differential, pipelined architecture with digital error correction and an on-chip sampleand-hold circuit to minimize power consumption and the external ponent count, while providing excellent dynamic performance. A unique sampleand-hold stage yields a full-power bandwidth of 1 GHz. The ADC14C105 may be operated from a single +3.0V or +3.3V power supply and consumes low power. A separate +2.5V supply may be used for the digital output interface which allows lower power operation with reduced noise. A power-down feature reduces the power consumption to very low levels while still allowing fast wake-up time to full operation. The differential inputs accept a 2V full scale differential input swing. A stable 1.2V internal voltage reference is provided, or the ADC14C105 can be operated with an external 1.2V reference. Output data format (offset binary versus 2's plement) and duty cycle stabilizer are pin-selectable. The duty cycle stabilizer maintains performance over a wide range of clock duty cycles. The ADC14C105 is available in a 32-lead WQFN package and operates...