Datasheet4U Logo Datasheet4U.com

ADS5546 - Analog-to-Digital Converters

General Description

ADS5546 is a high performance 14-bit, 190-MSPS A/D converter.

It offers state-of-the art functionality and performance using advanced techniques to minimize board space.

Key Features

  • Maximum Sample Rate: 190 MSPS.
  • 14-Bit Resolution.
  • No Missing Codes.
  • Total Power Dissipation 1.1 W.
  • Internal Sample and Hold.
  • 73.2-dBFS SNR at 70-MHz IF.
  • 87-dBc SFDR at 70-MHz IF, 0 dB gain.
  • Double Data Rate (DDR) LVDS and Parallel CMOS Output Options.
  • Programmable Gain up to 6 dB for SNR/SFDR Trade-Off at High IF.
  • Reduced Power Modes at Lower Sample Rates.
  • Supports input clock amplitude down to 40.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
ADS5541 Analog-to-Digital Converter Burr-Brown
ADS5542 Analog-to-Digital Converter Burr-Brown
ADS5510 125-MSPS Analog-To-Digital Converter Burr-Brown
ADS5522 Analog-to-Digital Converter Burr-Brown
ADS55A100H SCRs ADV

Other Datasheets by Texas Instruments

Part Number Description
ADS5545 Analog-to-Digital Converters
ADS5547 Analog-to-Digital Converters
ADS5500 Analog-to-Digital Converters
ADS5500-EP Analog-to-Digital Converters
ADS5517 Analog-to-Digital Converters

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
ADS5546 www.ti.com SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007 14-BIT, 190 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS FEATURES • Maximum Sample Rate: 190 MSPS • 14-Bit Resolution • No Missing Codes • Total Power Dissipation 1.1 W • Internal Sample and Hold • 73.2-dBFS SNR at 70-MHz IF • 87-dBc SFDR at 70-MHz IF, 0 dB gain • Double Data Rate (DDR) LVDS and Parallel CMOS Output Options • Programmable Gain up to 6 dB for SNR/SFDR Trade-Off at High IF • Reduced Power Modes at Lower Sample Rates • Supports input clock amplitude down to 400 mVPP • Clock Duty Cycle Stabilizer • No External Reference Decoupling Required • Internal and External Reference Support • Programmable Output Clock position to ease data capture • 3.