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ADS58J89 - Quad Channel 14-Bit 250/500 MSPS Receiver and Feedback

Datasheet Summary

Description

The ADS58J89 is a high-linearity, quad-channel, 14bit, 250/500-MSPS IF (intermediate frequency) receiver.

The four channels contain 500MSPS 14-bit ADCs followed by signal processing for wireless infrastructure systems.

Features

  • 1 4-Ch, 14-Bit 500MSPS With Digital Signal Processing.
  • Power Amplifier Linearization (Feedback) Modes.
  • 14-Bits Every Other Sample at 250MSPS.
  • Programmable Resolution vs Duty Cycle.
  • Duty Cycle 3:2 (60% 11-Bit, 40% 9-Bit).
  • Duty Cycle 2:3 (40% 12-Bit, 60% 9-Bit).
  • Duty Cycle 1:3 (25% 14-Bit, 75% 9-Bit).
  • Traffic Receiver Modes.
  • 14-Bit 250MSPS: Decimate by 2 Filter, High/Low Pass.
  • 9-Bit SNR-Boost Filter (150-MHz.

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Datasheet Details

Part number ADS58J89
Manufacturer Texas Instruments
File Size 2.48 MB
Description Quad Channel 14-Bit 250/500 MSPS Receiver and Feedback
Datasheet download datasheet ADS58J89 Datasheet
Additional preview pages of the ADS58J89 datasheet.

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Product Folder Sample & Buy Technical Documents Tools & Software Support & Community ADS58J89 SBAS659 – NOVEMBER 2014 ADS58J89 Quad Channel 14-Bit 250/500 MSPS Receiver and Feedback IC 1 Features •1 4-Ch, 14-Bit 500MSPS With Digital Signal Processing • Power Amplifier Linearization (Feedback) Modes – 14-Bits Every Other Sample at 250MSPS – Programmable Resolution vs Duty Cycle – Duty Cycle 3:2 (60% 11-Bit, 40% 9-Bit) – Duty Cycle 2:3 (40% 12-Bit, 60% 9-Bit) – Duty Cycle 1:3 (25% 14-Bit, 75% 9-Bit) • Traffic Receiver Modes – 14-Bit 250MSPS: Decimate by 2 Filter, High/Low Pass – 9-Bit SNR-Boost Filter (150-MHz Max Bandwidth) – 9-to-14-Bit TDD Burst (200-MHz Max Bandwidth) • Flexible Input Clock Buffer With Divide by 1/2/4 • JESD204B Digital Interface up to 5.
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