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ADS6125 - Analog-to-Digital Converters

Download the ADS6125 datasheet PDF. This datasheet also covers the ADS6122 variant, as both devices belong to the same analog-to-digital converters family and are provided as variant models within a single manufacturer datasheet.

General Description

ADS6125/ADS6124/ADS6123/ADS6122 (ADS612X) is a family of 12-bit A/D converters with sampling frequencies up to 125 MSPS.

It combines high performance and low power consumption in a compact 32 QFN package.

Key Features

  • 1.
  • Maximum Sample Rate: 125 MSPS.
  • 12-Bit Resolution with No Missing Codes.
  • 3.5 dB Coarse Gain and up to 6 dB Programmable Fine Gain for SNR/SFDR Trade-Off.
  • Parallel CMOS and Double Data Rate (DDR) LVDS Output Options.
  • Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Clock Amplitude Down to 400 mVPP.
  • Clock Duty Cycle Stabilizer.
  • Internal Reference with Support for External Reference.
  • No External Decoupling Required for Re.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (ADS6122-etcTI.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Texas Instruments

Part Number Description
ADS6122 Analog-to-Digital Converters
ADS6123 Analog-to-Digital Converters
ADS6124 Analog-to-Digital Converters
ADS6128 Analog-to-Digital Converters
ADS6129 Analog-to-Digital Converters

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
www.ti.com ADS6125, ADS6124 ADS6123, ADS6122 SLAS560A – OCTOBER 2007 – REVISED MARCH 2008 12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS FEATURES 1 • Maximum Sample Rate: 125 MSPS • 12-Bit Resolution with No Missing Codes • 3.5 dB Coarse Gain and up to 6 dB Programmable Fine Gain for SNR/SFDR Trade-Off • Parallel CMOS and Double Data Rate (DDR) LVDS Output Options • Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Clock Amplitude Down to 400 mVPP • Clock Duty Cycle Stabilizer • Internal Reference with Support for External Reference • No External Decoupling Required for References • Programmable Output Clock Position and Drive Strength to Ease Data Capture • 3.3 V Analog and 1.8 V to 3.