Datasheet4U Logo Datasheet4U.com

ADS6422 - Analog-to-Digital Converters

General Description

The ADS6424/ADS6423/ADS6422 (ADS642X) is a family of high performance 12-bit 105/80/65 MSPS quad channel A-D converters.

Serial LVDS data outputs reduce the number of interface lines, resulting in a compact 64-pin QFN package (9 mm × 9 mm) that allows for high system integration density.

Key Features

  • 1.
  • 12-Bit Resolution With No Missing Codes.
  • Simultaneous Sample and Hold.
  • 3.5dB Coarse Gain and upto 6dB Programmable Fine Gain for SFDR/SNR TradeOff.
  • Serialized LVDS Outputs With Programmable Internal Termination Option.
  • Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Amplitude down to 400 mVPP.
  • Internal Reference With External Reference Support.
  • No External Decoupling Required for References.
  • 3.3-V Analog and Digital.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
ADS60C100L 3 Quadrants Triacs ADV
ADS60C100S 3 Quadrants Triacs ADV
ADS60C120L 3 Quadrants Triacs ADV
ADS60C120S 3 Quadrants Triacs ADV
ADS60C160L 3 Quadrants Triacs ADV

Other Datasheets by Texas Instruments

Part Number Description
ADS6423 Analog-to-Digital Converters
ADS6424 Analog-to-Digital Converters
ADS6425 Analog-to-Digital Converters
ADS6442 Analog-to-Digital Converters
ADS6443 Analog-to-Digital Converters

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
www.ti.com ADS6424 ADS6423 ADS6422 SLAS532B – MAY 2007 – REVISED DECEMBER 2013 QUAD CHANNEL, 12-BIT, 105/80/65 MSPS ADC WITH SERIAL LVDS INTERFACE Check for Samples: ADS6424, ADS6423, ADS6422 FEATURES 1 • 12-Bit Resolution With No Missing Codes • Simultaneous Sample and Hold • 3.5dB Coarse Gain and upto 6dB Programmable Fine Gain for SFDR/SNR TradeOff • Serialized LVDS Outputs With Programmable Internal Termination Option • Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Amplitude down to 400 mVPP • Internal Reference With External Reference Support • No External Decoupling Required for References • 3.