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AM2632-Q1 - Microcontrollers

Download the AM2632-Q1 datasheet PDF. This datasheet also covers the AM2634 variant, as both devices belong to the same microcontrollers family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • Processor Cores:.
  • Single, dual, and quad-core Arm® Cortex®-R5F MCU with each core running up to 400MHz.
  • 16KB I-cache with 64-bit ECC per CPU core.
  • 16KB D-cache with 32-bit ECC per CPU core.
  • 64KB Tightly-Coupled Memory (TCM) with 32bit ECC per CPU core.
  • Lockstep or Dual-core capable clusters Memory Subsystem:.
  • 2MB of On-Chip RAM (OCSRAM).
  • 4 Banks x 512KB.
  • ECC error protection.
  • Internal DMA engine support System on Ch.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (AM2634-etcTI.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

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AM2615 Dual Differential Line Receivers AMD
AM2617 Quad RS-232C Line Receiver AMD
AM26LS29 Quad 3 State Single Ended RS-423 Line Driver AMD

Other Datasheets by Texas Instruments

Part Number Description
AM2632 Microcontrollers
AM2631 Microcontrollers
AM2631-Q1 Microcontrollers
AM2634 Microcontrollers
AM2634-Q1 Microcontrollers

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
AM2634, AM2634-Q1, AM2632, AM2632-Q1, AM2631, AM2631-Q1 SPRSP74E – OCTOBER 2022 – REVISED AUGUST 2025 AM263x Sitara™ Microcontrollers with Real-Time Control 1 Features Processor Cores: • Single, dual, and quad-core Arm® Cortex®-R5F MCU with each core running up to 400MHz – 16KB I-cache with 64-bit ECC per CPU core – 16KB D-cache with 32-bit ECC per CPU core – 64KB Tightly-Coupled Memory (TCM) with 32bit ECC per CPU core – Lockstep or Dual-core capable clusters Memory Subsystem: • 2MB of On-Chip RAM (OCSRAM) – 4 Banks x 512KB – ECC error protection – Internal DMA engine support System on Chip (SoC) Services and Architecture: • 1x EDMA to support data movement functions • Device Boot supported from the following interfaces: – UART (Primary/Backup) – QSPI NOR Flash (4S/1S) (Primary) • Interp