AM62P-Q1 Datasheet | Texas Instruments

Features Processor Cores: - Up to Quad 64-bit Arm® Cortex®-A53 microprocessor subsystem at up to 1.4GHz - Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC - Each A53 core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection - Single-core Arm® Cortex®-R5F at up to 800MHz, integrated as part of MCU Channel with FFI - 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories - 512KB SRAM with SECDED ECC - Single-core Arm® Cortex®-R5F at up to 800MHz, integrated to support Device Management - 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories Multimedia: - Display subsystem - Triple display support over OLDI (LVDS) (1x OLDI-DL, 1x or 2x OLDI-SL), DSI or DPI - OLDI-SL (Single Link): up to 1920 x 1080 at 60fps (165MHZ Pixel Clock) - OLDI-DL (Dual Link): up to 3840 x 1080 at 60fps (150MHz Pixel Clock) - MIPI® DSI: with 4 Lane MIPI® D-PHY supports up to 3840 x 1080 at 60fps (300MHz Pixel Clock) - DPI (24-bit RGB parallel interface): up to 1920 x 1080 at 60fps (165MHz pixel clock) - Four display pipelines with hardware overlay support. A maximum of two display pipelines may be used per display. - Supports safety features such as freeze frame detection and data correctness check - 3D Graphics Processing Unit - IMG BXS-4-64 with 256KB cache - Up to 50GFLOPS - Single shader core - Open GL ES3.2 and Vulkan 1.2 API support - One Camera Serial Interface (CSI-2) Receiver with 4 Lane D-PHY - MIPI® CSI-2 v1.3 pliant + MIPI D-PHY 1.2 - Support for 1,2,3 or 4 data lane mode up to 1.5Gbps per lane - ECC verification/correction with CRC check + ECC on RAM - Virtual Channel support (up to 16) - Ability to write stream data directly to DDR via - Video Encoder/Decoder - Support for HEVC (H.265) Main profiles at Level 5.1 High-tier - Support for H.264 Base Line/Main/High Profiles at Level 5.2 - Support for up to 4K UHD resolution (3840 × 2160) - Up to 300MPixels/s operation, with reduced clocking...