AM62P Description
ADVANCE INFORMATION AM62P, AM62P-Q1 SPRSP89A DECEMBER 2023 REVISED DECEMBER 2024 AM62Px Sitara™ Processors.
AM62P Key Features
- Up to Quad 64-bit Arm® Cortex®-A53 microprocessor subsystem at up to 1.4GHz
- Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC
- Each A53 core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection
- Single-core Arm® Cortex®-R5F at up to 800MHz, integrated as part of MCU Channel with FFI
- 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
- 512KB SRAM with SECDED ECC
- Single-core Arm® Cortex®-R5F at up to 800MHz
- 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
- Display subsystem
- Triple display support over OLDI (LVDS) (1x OLDI-DL, 1x or 2x OLDI-SL), DSI or DPI
AM62P Applications
- Up to 1.09MB of On-chip RAM
- 64KB of On-Chip RAM (OCRAM) with SECDED ECC, can be divided into smaller banks in increments of 32KB for as many as 2 separate memory banks
- 256KB of On-Chip RAM with SECDED ECC in SMS Subsystem
- 176KB of On-Chip RAM with SECDED ECC in SMS Subsystem for TI security firmware
- 512KB of On-chip RAM with SECDED ECC in Cortex-R5F MCU Subsystem
- 64KB of On-chip RAM with SECDED ECC in Device Manager Subsystem