CD54ACT191 Datasheet | Texas Instruments

Features - Buffered Inputs - Typical Propagation Delay - 12.8ns at VCC = 5V, TA = 25o C, CL = 50p F - Exceeds 2k V ESD Protection MIL-STD-883, Method 3015 - SCR-Latchup-Resistant CMOS Process and Circuit Design - Speed of Bipolar FAST™/AS/S with Significantly Reduced Power Consumption - Balanced Propagation Delays - AC Types Feature 1.5V to 5.5V Operation and Balanced Noise Immunity at 30% of the Supply - ±24m A Output Drive Current - Fanout to 15 FAST™ ICs - Drives 50Ω Transmission Lines Description The CD54AC191 and CD54ACT191 are asynchronously presettable binary up/down synchronous counters that utilize Advanced CMOS Logic technology. Presetting the counter to the number on preset data inputs (P0-P3) is acplished by setting LOW the asynchronous parallel load input (PL). Counting occurs when PL is HIGH, Count Enable (CE) is LOW, and the Up/Down (U/D) input is either LOW for upcounting or HIGH for down-counting. The counter is incremented or decremented synchronously with the LOW-to HIGH transition of the clock. When an overflow or underflow of the counter occurs, the Terminal Count (TC) output, which is LOW during counting, goes HIGH and remains HIGH for one clock cycle. This output can be used for look-ahead carry in high-speed cascading (see Figure 12). The TC output also initiates the Ripple Clock (RC) output which, normally HIGH, goes LOW and remains LOW for the low-level cascaded using the Ripple Count output. Ordering Information Pinout PART NUMBER TEMP. RANGE (o C) PACKAGE CD54AC191F3A -55 to 125 16 Ld CERDIP CD54ACT191F3A -55 to 125 16 Ld CERDIP NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer and die for this part number is available which meets all electrical specifications. Please contact your local TI sales office or customer service for ordering information. CD54AC191, CD54ACT191 (CERDIP) TOP VIEW P1 1 Q1 2 Q0 3 CE 4 U/D 5 Q2 6 Q3 7 GND 8 16 VCC 15 P0 14 CP 13 RC 12 TC...