Texas Instruments CD54HC192
The ’HC192, ’HC193 and ’HCT193 are asynchronously presettable BCD Decade and Binary Up/Down synchronous counters, respectively. The counter is incremented on the low-to-high transition of the Clock-Up input (and a high level on the ClockDown input) and decremented on the low to high transition of the Clock-Down input (and a high level on the Clock-up input).| Part No. | CD54HC192 |
|---|---|
| Datasheet | CD54HC192 Download |
| Manufacturer |  Texas Instruments |
| Description | Presettable Synchronous 4-Bit Up/Down Counters |
| Buy | Stock & Price |
FEATURES
● Synchronous Counting and Asynchronous Loading● Two Outputs for N-Bit Cascading
● Look-Ahead Carry for High-Speed Counting
● Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
● Wide Operating Temperature Range . . . -55oC to 125oC
● Balanced Propagation Delay and Transition Times
● Significant Power Reduction Compared to LSTTL Logic ICs
● HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
● HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
DESCRIPTION
Presetting the counter to the number on the preset data inputs (P0-P3) is accomplished by a LOW asynchronous parallel load input (PL). A high level on the MR input overrides any other input to clear the counter to its zero state. The Terminal Count up (carry) goes low half a clock period before the zero count is reached and returns to a high level at the zero count.
