CD54HCT00J Description
This device contains four independent 2-input NAND gates. Each gate performs the Boolean function Y = A B in positive logic. CD74HCT00 CD54HCT00 CD74HCT00, CD54HCT00 SCHS398 JANUARY 2021 .ti.
CD54HCT00J Key Features
- LSTTL input logic patible
- VIL(max) = 0.8 V, VIH(min) = 2 V
- CMOS input logic patible
- II ≤ 1 µA at VOL, VOH
- Buffered inputs
- 4.5 V to 5.5 V operation
- Wide operating temperature range
- 55°C to +125°C
- Supports fanout up to 10 LSTTL loads
- Significant power reduction pared to LSTTL