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CD54HCT4017 - DECADE COUNTER/DIVIDER

General Description

The CD54HCT4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs.

Each decoded output normally is low and sequentially goes high on the low-to-high transition of the clock (CP) input.

Each output stays high for one clock period of the ten-clock-period cycle.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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D 4.5-V to 5.5-V Operation D Fully Static Operation D Buffered Inputs D Common Reset D Positive-Edge Clocking D Balanced Propagation Delay and Transition Times D Direct LSTTL Input Logic Compatibility – VIL = 0.8 V Maximum; VIH = 2 V Minimum D CMOS Input Compatibility – II ≤ 1 µA at VOL, VOH D Packaged in Ceramic (F) DIP Packages and Also Available in Chip Form (H) CD54HCT4017 DECADE COUNTER/DIVIDER WITH TEN DECODED OUTPUTS SGDS012 – MAY 1999 F PACKAGE (TOP VIEW) 5 1 0 2 6 7 3 GND 1 2 3 4 5 6 7 8 16 VCC 15 MR 14 CP 13 CE 12 TC 11 9 10 4 98 description The CD54HCT4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each decoded output normally is low and sequentially goes high on the low-to-high transition of the clock (CP) input.