CD54HCT4024 Datasheet | Texas Instruments

Data sheet acquired from Harris Semiconductor SCHS202C November 1997 - Revised October 2003 CD54HC4024, CD74HC4024, CD54HCT4024, CD74HCT4024 High-Speed CMOS Logic 7-Stage Binary Ripple Counter [ /Title (CD74 HC402 4, CD74 HCT40 24) /Subject (High Speed CMOS Features Description - Fully Static Operation - Buffered Inputs - mon Reset - Negative Edge Clocking - Fanout (Over Temperature Range) - Standard Outputs - - - 10 LSTTL Loads - Bus Driver Outputs - - . . . 15 LSTTL Loads - Wide Operating Temperature Range . . . -55o C to 125o C - Balanced Propagation Delay and Transition Times - Significant Power Reduction pared to LSTTL Logic ICs - HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V - HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic patibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input patibility, Il ≤ 1µA at VOL, VOH The ’HC4024 and ’HCT4024 are 7-stage ripple-carry binary counters. All counter stages are master-slave flip-flops. The state of the stage advances one count on the negative transition of each input pulse; a high voltage level on the MR line resets all counters to their zero state. All inputs and outputs are buffered. Ordering...