Datasheet4U Logo Datasheet4U.com

CD74AC138 - 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

Datasheet Summary

Description

The ’AC138 decoders/demultiplexers are designed for high-performance memory-decoding and data-routing applications that require very short propagation-delay times.

In high-performance memory systems, these decoders can be used to minimize the effects of system decoding.

📥 Download Datasheet

Datasheet preview – CD74AC138

Datasheet Details

Part number CD74AC138
Manufacturer Texas Instruments
File Size 512.17 KB
Description 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
Datasheet download datasheet CD74AC138 Datasheet
Additional preview pages of the CD74AC138 datasheet.

📁 Similar Datasheet

  • CD7401 - Speaker (Turbosonic)
  • CD746A - ZENER DIODE (Compensated Deuices)
  • CD746A - ZENER DIODE CHIPS (Deuices Incorporated)
  • CD747A - ZENER DIODE (Compensated Deuices)
  • CD747A - ZENER DIODE CHIPS (Deuices Incorporated)
  • CD748A - ZENER DIODE (Compensated Deuices)
  • CD748A - ZENER DIODE CHIPS (Deuices Incorporated)
  • CD749A - ZENER DIODE (Compensated Deuices)
  • CD749A - ZENER DIODE CHIPS (Deuices Incorporated)
  • CD74FCT2245T - Fast CMOS Octal Bidirectional Transceivers (Harris Semiconductor)
Other Datasheets by Texas Instruments
  • CD74AC139 - DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS
  • CD74AC10 - TRIPLE 3-INPUT POSITIVE-NAND GATES
  • CD74AC109 - DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
  • CD74AC112 - DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
  • CD74AC14 - Hex Schmitt-Trigger Inverter
  • CD74AC151 - 8-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER
  • CD74AC153 - DUAL 4-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS
  • CD74AC157 - QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS

Full PDF Text Transcription

Click to expand full text
CD54AC138, CD74AC138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS D AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Voltage D Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption D Designed Specifically for High-Speed Memory Decoders and Data-Transmission Systems D Incorporate Three Enable Inputs to Simplify Cascading and/or Data Reception D Balanced Propagation Delays D ±24-mA Output Drive Current – Fanout to 15 F Devices D SCR-Latchup-Resistant CMOS Process and Circuit Design D Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015 SCHS328A – JANUARY 2003 – REVISED FEBRUARY 2003 CD54AC138 . . . F PACKAGE CD74AC138 . . .
Published: |