CD74AC138 Datasheet | Texas Instruments

Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Voltage D Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption D Designed Specifically for High-Speed Memory Decoders and Data-Transmission Systems D Incorporate Three Enable Inputs to Simplify Cascading and/or Data Reception D Balanced Propagation Delays D ±24-m A Output Drive Current - Fanout to 15 F Devices D SCR-Latchup-Resistant CMOS Process and Circuit Design D Exceeds 2-k V ESD Protection Per MIL-STD-883, Method 3015 SCHS328A - JANUARY 2003 - REVISED FEBRUARY 2003 CD54AC138 . . . F PACKAGE CD74AC138 . . . E OR M PACKAGE (TOP VIEW) A1 B2 C3 G2A 4 G2B 5 G1 6 Y7 7 GND 8 16 VCC 15 Y0 14 Y1 13 Y2 12 Y3 11 Y4 10 Y5 9 Y6 description /ordering information The ’AC138 decoders/demultiplexers are designed for high-performance memory-decoding and data-routing applications that require very short propagation-delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible. The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications (see Application Information). ORDERING INFORMATION PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP - E Tube CD74AC138E CD74AC138E - 55°C to 125°C SOIC - M Tube CD74AC138M...