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CD74ACT297 - DIGITAL PHASE-LOCKED LOOP

General Description

The CD74ACT297 provides a simple, cost-effective solution to high-accuracy, digital, phase-locked-loop applications.

This device contains all the necessary circuits, with the exception of the divide-by-N counter, to build first-order phase-locked loops as shown in Figure 1.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CD74ACT297 DIGITAL PHASE-LOCKED LOOP D Speed of Bipolar FCT, AS, and S, With Significantly Reduced Power Consumption D Digital Design Avoids Analog Compensation Errors D Easily Cascadable for Higher-Order Loops D Useful Frequency Range – DC to 110 MHz Typical (K CLK) – DC to 70 MHz Typical (I/D CLK) D Dynamically Variable Bandwidth D Very Narrow Bandwidth Attainable D Power-On Reset D Output Capability – Standard: XORPD OUT, ECPD OUT – Bus Driver: I/D OUT D SCR Latch-Up-Resistant CMOS Process and Circuit Design D Balanced Propagation Delays D ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015 SCHS297D – AUGUST 1998 – REVISED JUNE 2002 M PACKAGE (TOP VIEW) B1 A2 ENCTR 3 K CLK 4 I/D CLK 5 D/U 6 I/D OUT 7 GND 8 16 VCC 15 C 14 D 13 φA2 12 ECPD OUT 11 XORPD OUT 10 φB 9 φA1 descript