CD74HC175 Datasheet | Texas Instruments

Features - mon Clock and Asynchronous Reset on Four D-Type Flip-Flops - Positive Edge Pulse Triggering - plementary Outputs - Buffered Inputs - Fanout (Over Temperature Range) - Standard Outputs - - - 10 LSTTL Loads - Bus Driver Outputs - - . . . 15 LSTTL Loads - Wide Operating Temperature Range . . . -55o C to 125o C - Balanced Propagation Delay and Transition Times - Significant Power Reduction pared to LSTTL Logic ICs - HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V - HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic patibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input patibility, Il ≤ 1µA at VOL, VOH Description advantage of standard CMOS ICs and the ability to drive 10 LSTTL devices. Information at the D input is transferred to the Q, Q outputs on the positive going edge of the clock pulse. All four Flip-Flops are controlled by a mon clock (CP) and a mon reset (MR). Resetting is acplished by a low voltage level independent of the clock. All four Q outputs are reset to a logic 0 and all four Q outputs to a logic 1. Ordering Information PART NUMBER CD54HC175F3A CD54HCT175F3A CD74HC175E CD74HC175M CD74HC175MT CD74HC175M96 CD74HCT175E CD74HCT175M CD74HCT175MT CD74HCT175M96 TEMP. RANGE (o C) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld CERDIP 16 Ld CERDIP 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC The ’HC175 and ’HCT175 are high speed Quad D-type Flip Flops with individual D-inputs and Q, Q plementary outputs. The devices are fabricated using silicon gate CMOS technology. They have the low power consumption NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. Pinout CD54HC175, CD54HCT175 (CERDIP) CD74HC175, CD74HCT175 (PDIP, SOIC) TOP VIEW MR 1 Q0 2 Q0 3 D0...