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CD74HC4017-Q1 - HIGH-SPEED CMOS LOGIC DECADE COUNTER/DIVIDER

General Description

outputs.

and sequentially goes high on the low-to-high transition clock period of the ten-clock-period cycle.

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CD74HC4017-Q1 HIGH-SPEED CMOS LOGIC DECADE COUNTER/DIVIDER WITH 10 DECODED OUTPUTS SCLS546SA − OCTOBER 2003 − REVISED APRIL 2008 D Qualified for Automotive Applications D Significant Power Reduction Compared to D Fully Static Operation D Buffered Inputs D Common Reset D Positive Edge Clocking LSTTL Logic ICs D VCC Voltage = 2 V to 6 V D High Noise Immunity NIL or NIH = 30% of VCC, VCC = 5 V D Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25°C D Fanout (Over Temperature Range) − Standard Outputs . . . 10 LSTTL Loads − Bus Driver Outputs . . .