CD74HCT563 Datasheet | Texas Instruments

Features Description - mon Latch-Enable Control - mon Three-State Output Enable Control - Buffered Inputs - Three-State Outputs - Bus Line Driving Capacity - TCy Lp=ic1a5l p PFr,o Tp Aag=a2ti5oon CD(e Dlaatya=to13Onustpaut t V) CC = 5V, - Fanout (Over Temperature Range) - Standard Outputs - - - 10 LSTTL Loads - Bus Driver Outputs - - . . . 15 LSTTL Loads - Wide Operating Temperature Range . . . -55o C to 125o C - Balanced Propagation Delay and Transition Times - Significant Power Reduction pared to LSTTL Logic ICs - HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V - HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic patibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input patibility, Il ≤ 1µA at VOL, VOH The ’HC533, ’HCT533, ’HC563, and CD74HCT563 are high-speed Octal Transparent Latches manufactured with silicon gate CMOS technology. They possess the low power consumption of standard CMOS integrated circuits, as well as the ability to drive 15 LSTTL devices. The outputs are transparent to the inputs when the latch enable (LE) is high. When the latch enable (LE) goes low the data is latched. The output enable (OE) controls the three-state outputs. When the output enable (OE) is high the outputs are in the high impedance state. The latch operation is independent of the state of the output enable. The ’HC533 and ’HCT533 are identical in function to the ’HC563 and CD74HCT563 but have different pinouts. The ’HC533 and ’HCT533 are similar to the ’HC373 and ’HCT373; the latter are non-inverting types. Ordering Information PART NUMBER CD54HC533F3A CD54HC563F3A CD54HCT533F3A CD74HC533E CD74HC563E CD74HC563M CD74HCT533E CD74HCT563E CD74HCT563M TEMP. RANGE (o C) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 20 Ld CERDIP 20 Ld CERDIP 20 Ld CERDIP 20 Ld PDIP 20 Ld PDIP 20 Ld SOIC 20 Ld PDIP 20 Ld PDIP 20 Ld SOIC CAUTION: These...