CD74HCT73 Datasheet | Texas Instruments

Features Description - Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times - Asynchronous Reset - plementary Outputs - Buffered Inputs - TTAyp=ic2a5lof CMAX = 60MHz at VCC = 5V, CL = 15p F, - Fanout (Over Temperature Range) - Standard Outputs - - - 10 LSTTL Loads - Bus Driver Outputs - - . . . 15 LSTTL Loads - Wide Operating Temperature Range . . . -55o C to 125o C - Balanced Propagation Delay and Transition Times The ’HC73 and CD74HCT73 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads. These flip-flops have independent J, K, Reset and Clock inputs and Q and Q outputs. They change state on the negative-going transition of the clock pulse. Reset is acplished asynchronously by a low level input. This device is functionally identical to the HC/HCT107 but differs in terminal assignment and in some parametric limits. The HCT logic family is functionally as well as pin patible with the standard LS logic family. Ordering Information - Significant Power Reduction pared to LSTTL Logic ICs - HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V - HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic patibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input patibility, Il ≤ 1µA at VOL, VOH PART NUMBER TEMP. RANGE (o C) PACKAGE CD54HC73F3A -55 to 125 14 Ld CERDIP CD74HC73E -55 to 125 14 Ld PDIP CD74HC73M -55 to 125 14 Ld SOIC CD74HC73MT...