CDCE72010 Description
SCAS858C JUNE 2008 REVISED JANUARY 2012 Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor Check for Samples:.
CDCE72010 Key Features
- High Performance LVPECL, LVDS, LVCMOS PLL Clock Synchronizer
- Two Reference Clock Inputs (Primary and Secondary Clock) for Redundancy Support with Manual or Automatic Selection
- Accepts Two Differential Input (LVPECL or LVDS) References up to 500MHz (or Two LVCMOS Inputs up to 250MHz) as PLL Refer
- VCXO_IN Clock is Synchronized to One of Two Reference Clocks
- VCXO_IN Frequencies up to 1.5GHz (LVPECL) 800MHz for LVDS and 250MHz for LVCMOS Level Signaling
- Outputs Can be a bination of LVPECL, LVDS, and LVCMOS (Up to 10 Differential LVPECL or LVDS Outputs or up to 20 LVCMOS O
- SPI Controllable Device Setting
- Individual Output Enable Control via SPI Interface
- Integrated On-Chip Non-Volatile Memory (EEPROM) to Store Settings without the Need to Apply High Voltage to the Device
- Optional Configuration Pins to Select Between Two Default Settings Stored in EEPROM
CDCE72010 Applications
- Low Jitter Clock Driver for High-End Tele and Wireless Applications