CDCLVD110 Overview
The CDCLVD110 clock driver distributes one pair of differential LVDS clock inputs (either CLK0 or CLK1) to 10 pairs of differential clock outputs (Q0, Q9) with minimum skew for clock distribution. The CDCLVD110 is specifically designed for driving 50-Ω transmission lines. When the control enable is high (EN = 1), the 10 differential outputs are programmable in that each output can be individually enabled/disabled...
CDCLVD110 Key Features
- Low-Output Skew <30 ps (Typical) for Clock-Distribution
CDCLVD110 Applications
- Distributes One Differential Clock Input to 10 LVDS Differential Clock Outputs