CDCLVD110A Overview
The CDCLVD110A clock driver distributes one pair of differential LVDS clock inputs (either CLK0 or CLK1) to 10 pairs of differential clock outputs (Q0 to Q9) with minimum skew for clock distribution. The CDCLVD110A is specifically designed to drive 50-Ω transmission lines. When the control enable is high (EN = 1), the 10 differential outputs are programmable in that each output can be individually enabled or...
CDCLVD110A Key Features
- 1 Low-Output Skew <30 ps (Typical) for ClockDistribution
CDCLVD110A Applications
- Distributes One Differential Clock Input to 10 LVDS Differential Clock Outputs