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CDCLVD110A - PROGRAMMABLE LOW-VOLTAGE 1:10 LVDS CLOCK DRIVER

General Description

The CDCLVD110A clock driver distributes one pair of differential LVDS clock inputs (either CLK0 or CLK1) to 10 pairs of differential clock outputs (Q0 to Q9) with minimum skew for clock distribution.

The CDCLVD110A is specifically designed to drive 50-Ω transmission lines.

Key Features

  • 1 Low-Output Skew.

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CDCLVD110 PROGRAMMABLE LOW-VOLTAGE 1:10 LVDS CLOCK DRIVER
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Product Folder Sample & Buy Technical Documents Tools & Software Support & Community CDCLVD110A SCAS841D – FEBRUARY 2007 – REVISED DECEMBER 2016 CDCLVD110A Programmable Low-Voltage 1:10 LVDS Clock Driver 1 Features •1 Low-Output Skew <30 ps (Typical) for ClockDistribution Applications • Distributes One Differential Clock Input to 10 LVDS Differential Clock Outputs • VCC Range: 2.5 V ±5% • Typical Signaling Rate Capability of Up to 1.