CDCLVD110A
Overview
The CDCLVD110A clock driver distributes one pair of differential LVDS clock inputs (either CLK0 or CLK1) to 10 pairs of differential clock outputs (Q0 to Q9) with minimum skew for clock distribution. The CDCLVD110A is specifically designed to drive 50-Ω transmission lines.
- 1 Low-Output Skew <30 ps (Typical) for ClockDistribution Applications
- Distributes One Differential Clock Input to 10 LVDS Differential Clock Outputs
- VCC Range: 2.5 V ±5%
- Typical Signaling Rate Capability of Up to
- 1 GHz
- Configurable Register (SI/CK) Individually Enables Disables Outputs, Selectable CLK0, CLK0 or CLK1, CLK1 Inputs
- Full Rail-to-Rail Common-Mode Input Range
- Receiver Input Threshold: ±100 mV
- Available in 32-Pin LQFP and VQFN Package
- Fail-Safe I/O-Pins for VDD = 0 V (Power Down)
