CDCLVP1204 Overview
The CDCLVP1204 is a highly versatile, low additive jitter buffer that can generate four copies of LVPECL clock outputs from one of two selectable LVPECL, LVDS, or LVCMOS inputs for a variety of munication applications. It has a maximum clock frequency up to 2 GHz.
CDCLVP1204 Key Features
- 1 2:4 Differential Buffer
- Selectable Clock Inputs Through Control Terminal
- Universal Inputs Accept LVPECL, LVDS, and
- Four LVPECL Outputs
- Maximum Clock Frequency: 2 GHz
- Maximum Core Current Consumption: 45 mA
- Very Low Additive Jitter: <100 fs, RMS in 10-kHz
- 57 fs, RMS (typical) at 122.88 MHz
- 48 fs, RMS (typical) at 156.25 MHz
- 30 fs, RMS (typical) at 312.5 MHz