Datasheet4U Logo Datasheet4U.com

CDCLVP1204 - High-Performance Clock Buffer

General Description

The CDCLVP1204 is a highly versatile, low additive jitter buffer that can generate four copies of LVPECL clock outputs from one of two selectable LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications.

It has a maximum clock frequency up to 2 GHz.

The CDCLVP1204

Overview

Product Folder Sample & Buy Technical Documents Tools & Software Support & Community Reference Design CDCLVP1204 SCAS880F – AUGUST 2009 – REVISED SEPTEMBER 2015 CDCLVP1204 Four LVPECL Output, High-Performance Clock.

Key Features

  • 1 2:4 Differential Buffer.
  • Selectable Clock Inputs Through Control Terminal.
  • Universal Inputs Accept LVPECL, LVDS, and LVCMOS/LVTTL.
  • Four LVPECL Outputs.
  • Maximum Clock Frequency: 2 GHz.
  • Maximum Core Current Consumption: 45 mA.
  • Very Low Additive Jitter:.