CY74FCT2574T Datasheet | Texas Instruments

D Function and Pinout patible With FCT and F Logic D 25-Ω Output Series Resistors to Reduce Transmission-Line Reflection Noise D Reduced VOH (Typically = 3.3 V) Version of Equivalent FCT Functions D Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics D Ioff Supports Partial-Power-Down Mode Operation D Matched Rise and Fall Times D Fully patible With TTL Input and Output Logic Levels D ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) - 1000-V Charged-Device Model (C101) D 3-State Outputs D 12-m A Output Sink Current 15-m A Output Source Current D Edge-Triggered D-Type Inputs D 250-MHz Typical Switching Rate CY74FCT2574T 8-BIT REGISTER WITH 3-STATE OUTPUTS SCCS076 - OCTOBER 2001 Q OR SO PACKAGE (TOP VIEW) D0 D1 D2 D3 D4 D5 D6 D7 GND 1 2 3 4 5 6 7 8 9 10 20 VCC 19 O0 18 O1 17 O2 16 O3 15 O4 14 O5 13 O6 12 O7 11 CP description The CY74FCT2574T is a high-speed, low-power, octal D-type flip-flop featuring separate D-type inputs for each flip-flop. On-chip termination resistors at the outputs reduce system noise caused by reflections. The CY74FCT2574T can replace the CY74FCT574T to reduce noise in an existing design. This device has 3-state outputs for bus-oriented applications. A buffered clock (CP) and output-enable (OE) inputs are mon to all flip-flops. The CY74FCT2574T is identical to the CY74FCT2374T, except that on the CY74FCT2574T all outputs are on one side of the package and all inputs are on the other side. The flip-flops in the CY74FCT2574T store the state of their individual D inputs that meet the setup-time and hold-time requirements on the low-to-high CP transition. When OE is low, the contents of the flip-flops are available at the outputs. When OE is high, the outputs are in the high-impedance state. The state of OE does not affect the state of the flip-flops. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the...