DS34C86T Datasheet | Texas Instruments

FEATURES - 2 CMOS Design for Low Power - ±0.2V Sensitivity Over the Input mon Mode Voltage Range - Typical Propagation Delays: 19 ns - Typical Input Hysteresis: 60 m V - Inputs Won't Load Line when VCC = 0V - Meets the Requirements of EIA Standard RS- - TRI-STATE Outputs for System Bus patibility - Available in Surface Mount - Open Input Failsafe Feature , Output High for Open Input DESCRIPTION The DS34C86T is a quad differential line receiver designed to meet the RS-422, RS-423, and Federal Standards 1020 and 1030 for balanced and unbalanced digital data transmission, while retaining the low power characteristics of CMOS. The DS34C86T has an input sensitivity of 200 m V over the mon mode input voltage range of ±7V. Hysteresis is provided to improve noise margin and discourage output instability for slowly changing input waveforms. The DS34C86T features internal pull-up and pulldown resistors which prevent output oscillation on unused channels. Separate enable pins allow independent control of receiver pairs. The TRI-STATE outputs have 6 m A source and sink capability. The DS34C86T is pin patible with the DS3486. Logic Diagram Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1998- 2013, Texas Instruments Incorporated SNLS379C - MAY 1998 - REVISED APRIL 2013 Connection Diagram Top View .ti. Figure 1. PDIP Package See Package Numbers D0016A or NFG0016E Enable L H H H (1) Open, not terminated. Z = TRI-STATE Truth Table(1) Input X VID ≥ VTH (Max) VID ≤ VTH (Min) Open-...