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DS90C241 - 5-MHz to 35-MHz DC-Balanced 24-Bit FPD-Link II Serializer/Deserializer

General Description

The DS90C241 and DS90C124 chipset translates a 24-bit parallel bus into a fully transparent data and control LVDS serial stream with embedded clock information.

Key Features

  • 1 5-MHz to 35-MHz Clock Embedded and DCBalancing 24:1 and 1:24 Data Transmissions.
  • User Defined Pre-Emphasis Driving Ability Through External Resistor on LVDS Outputs and Capable to Drive Up to 10-Meter Shielded Twisted-Pair Cable.
  • User-Selectable Clock Edge for Parallel Data on Both Transmitter and Receiver.
  • Internal DC Balancing Encode and Decode (Supports AC-Coupling Interface With No External Coding Required).
  • Individual Power-Down Controls for Bo.

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Datasheet Details

Part number DS90C241
Manufacturer Texas Instruments
File Size 2.18 MB
Description 5-MHz to 35-MHz DC-Balanced 24-Bit FPD-Link II Serializer/Deserializer
Datasheet download datasheet DS90C241 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Product Folder Order Now Technical Documents Tools & Software Support & Community DS90C124, DS90C241 SNLS209M – NOVEMBER 2005 – REVISED JANUARY 2017 DS90C241 and DS90C124 5-MHz to 35-MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer 1 Features •1 5-MHz to 35-MHz Clock Embedded and DCBalancing 24:1 and 1:24 Data Transmissions • User Defined Pre-Emphasis Driving Ability Through External Resistor on LVDS Outputs and Capable to Drive Up to 10-Meter Shielded Twisted-Pair Cable • User-Selectable Clock Edge for Parallel Data on Both Transmitter and Receiver • Internal DC Balancing Encode and Decode (Supports AC-Coupling Interface With No External Coding Required) • Individual Power-Down Controls for Both Transmitter and Receiver • Embedded Clock CDR (Clock and Data Recovery) on