DS90C363B Overview
The DS90C363B transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted.
DS90C363B Key Features
- 23 No special start-up sequence required between clock/data and /PD pins. Input signal (clock and data) can be applied e
- Support Spread Spectrum Clocking up to 100kHz frequency modulation and deviations of ±2.5% center spread or -5% down spr
- "Input Clock Detection" feature will pull all LVDS pairs to logic low when input clock is missing and when /PD pin is lo
- 18 to 68 MHz shift clock support
- Best-in-Class Set & Hold Times on TxINPUTs
- Tx power consumption < 130 mW (typ) at
- 40% Less Power Dissipation than BiCMOS
- Tx Power-down mode < 37μW (typ)
- Supports VGA, SVGA, XGA and Dual Pixel
- Narrow bus reduces cable size and cost
