DS90C363B Datasheet | Texas Instruments

.ti. SNLS179F - APRIL 2004 - REVISED APRIL 2013 +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link -65 MHz Check for Samples: DS90C363B Features - 23 No special start-up sequence required between clock/data and /PD pins. Input signal (clock and data) can be applied either before or after the device is powered. - Support Spread Spectrum Clocking up to 100k Hz frequency modulation and deviations of ±2.5% center spread or - 5% down spread. - "Input Clock Detection" feature will pull all LVDS pairs to logic low when input clock is missing and when /PD pin is logic high. - 18 to 68 MHz shift clock support - Best- in- Class Set & Hold Times on Tx INPUTs - Tx power consumption < 130 m W (typ) at 65MHz Grayscale - 40% Less Power Dissipation than Bi CMOS Alternatives - Tx Power-down mode < 37μW (typ) - Supports VGA, SVGA, XGA and Dual Pixel SXGA. - Narrow bus reduces cable size and cost - Up to 1.3 Gbps throughput - Up to 170 Megabytes/sec bandwidth - 345 m V (typ) swing LVDS devices for low EMI - PLL requires no external ponents - patible with TIA/EIA-644 LVDS standard - Low profile 48-lead TSSOP package - Improved replacement for: - SN75LVDS84, DS90C363A DESCRIPTION...